Various factors that are considered for L1 cache memory include the size and performance of the type of memory used for implementing an L1 cache. In general, when L1 cache is embedded in a CPU (Central Processing Unit), its performance, e.g. access speed, must be compatible with CPU cycle time. Static random access memories (SRAMs) are primarily used for L1 cache memory as opposed to dynamic random access memories (DRAMs). Indeed, with respect to access speed, SRAM can provide access times of less than 1 ns, while the state-of-the-art DRAMs have access times ranging from 4 ns to 10 ns.
On the other hand, SRAM cells are typically formed with 6 transistors (i.e., 6T Cell), whereas DRAM cells are formed with one transistor and one capacitor. Therefore, memory arrays comprising SRAM cells are much larger than memory arrays comprising DRAM cells. Thus, the maximum capacity of the on-chip cache using SRAM is limited to less than 1M. Therefore, there is a need to increase the cache capacity to extend processor performance in areas such as networking, multimedia and communication.
SRAM design considerations are primarily determined by a particular application. For instance, high performance designs, such as for cache where read and write operations are performed within a short clock cycle, have cell beta ratios (which is defined as the ratio of channel resistance of the pass-gate device, also called transfer device, to that of driver device, also called pull-down device) that are typically around 2.2 to 3.5 to avoid cell disturbances, such as “half-selected cell disturbance,” which is well know in the art.
“Half selected cell disturbance” occurs when a word line connected to a memory cell of unselected columns with bit lines biased at a predetermined Vdd is activated. This causes the body voltage of a transfer device of a non-selected cell for a read or write operation along the activated wordline to rise and to be more conductive than a pull-down device, thereby causing a ground state node (“0” node) to switch logic states and disrupt the memory cell.
Typically, in a conventional methodology, a beta ratio is maintained by designing a W/L (width/Length) of the pull-down device over that of the pass-gate device to prevent the disturbance discussed above from effecting cell stability. For example, cells having a high beta ratio (3.5 or greater), will preserve data integrity via a resistive divider. Further, for slower designs, when a cell beta ratio ranges from 1.2 to 1.8, cell disturbances are not a problem because the operation speed of the cell is decreased by the slower devices having a higher Vt.
Depending on the cell structure, these devices can be either a NMOS or a PMOS transistor. For instance, in a 6-transistors SRAM with NMOS pass-gates and pull-down devices, the channel width of the pull-down device is increased to provide an increase in conductivity of the pull-down device thereby increasing the overall stability of the SRAM cell.
FIG. 1 is diagram illustrating a conventional structure of a 6T SRAM cell that comprises six MOS (or FET) transistors. Referring to FIG. 1, an SRAM cell 10 is shown. The SRAM cell (10) is shown to include four N-channel transistors (21A, 21B, 21C, and 21D). The SRAM cell (10) also includes two P-channel transistors (22A) and (22B). The source of transistor (21A) is connected to a first bit line (23), a gate of transistor (21A) is connected to a word line (26), and the drain of transistor (21A) is connected to a first node (27), wherein the first node (27) is connected to the source of transistor (21B) and the drain of transistor (22A). The source of transistor (21C) is connected to a second bit line (24), a gate of transistor (21C) is connected to the word line (26), and the drain of transistor (21C) is connected to a second node (28), wherein the second node (28) is connected to the source of transistor (21D) and the drain of transistor (22B). In addition, the source of transistors (22A) and (22B) are connected to a voltage source (25), and the drain of transistors (21B) and (21D) are connected to a ground (29). Further, the first node (27) is connected to the gate of transistors (21D) and (22B), and the second node (28) is connected to the gate of transistors (21B) and (22A), and wherein one of the storage nodes is pulled low and the other storage node is pulled high. As noted above, although 6T SRAM cells can provide high speed operation and can operate with low power supply voltage, 6T SRAM cells occupy a large area, thus limiting the memory cell density.
The following table shows the tabulated beta ratio vs. cell size in the 0.13 um generation designs:
TABLE 1Beta RatioCell SizeComments10.96Not useful with conventional approach1.51 (Normalized)Standard Cell in bulk CMOS2.251.07Standard SOI cells31.13High end designs3.751.2 Safe designs
Although, in fast switching environments, a SRAM array having a high beta ratio (e.g., 3.75 listed above in table 1) provides for better noise margins, the SRAM array having the high beta ratio requires a larger budget area that not only means higher cost, but also means a decrease in cell performance, such as slower write operation, and a limit on the memory cell density.
Further, a SRAM cell is built on a SOI (silicon on insulation) substrate having a beta ration of 1.50 fails to function properly. This is because SRAM cells built on a SOI substrate are sensitive to extra disturbances due to floating body effects. Even when a SRAM built on a SOI substrate is designed having a beta ratio, e.g., about 2.25, the SOI SRAM stability is still marginal. It has been determined that the floating body effects effectively reduce the beta ratio defined by the device dimension.
In other words, since bit-lines are constantly biased at Vdd, the body voltage of the transfer device tends to rise and to be more conductive than the pull-down device, which may cause the ground state node (“0” node) to switch logic states, e.g., switch from a logic state of “0” to a logic state “1.” Currently, the solution is simply to increase the width of the channel of the pull-down device to lower its threshold voltage (Vt). However, this increases the SRAM cell size which then increases the overall design area budget of a chip.
In FIG. 2, a conventional cell having a beta ratio of two, which ensures minimal cell stability from SRAM in the bulk substrate is shown. A SRAM on a SOI substrate having a higher beta ratio may be desirable because of an increase in stability, but there is also an increase in the size of the SRAM array that increase the area budget of the overall chip layout.
Now referring to FIG. 2, FIG. 2 shows a conventional 6T SRAM layout with passgates having a Voltage threshold of 0.3 V, a beta of 2, cell size of 2.65 um2, and Ldesign of 0.12 um. In addition, RX is the active silicon, PC is polysilicon, and NW is the nwell for the PFETs, P1 and P2. P1 and P2 are pull-up devices. N1 and N2 are pull-down devices, NFETs, having a W/L of about 0.36 um and about 0.12 um, respectively. Further, NL and NR are the left and right passgate devices, NFETs, having a W/L of about 0.18 um and about 0.12 um, respectively.
Therefore, a need exists to increase the cache capacity on a chip to extend processor performance in areas such as networking, multimedia and communication, while keeping within the designated area budget of the overall chip design and increasing the SRAMs stability.